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#define | CAN_RX_ENABLE PIER10 |
| Input enable register which contains the CAN input pin.
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#define | CAN_RX_BIT 0 |
| Bit in the input enable register of the CAN input pin.
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#define | CAN_BASE CTRLR0 |
| Base register of the CAN controller to be used (CTRLRx)
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#define | CAN_BUFFERCOUNT 32 |
| Number of CAN buffers in the CAN engine of the controller.
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#define | CANREG(x) (*((CAN_##x##_TYPE*)((uint8_t*)(&(CAN_BASE)) + CAN_##x##_OFFSET))) |
| Calculates the register (including appropriate type) based on CAN_BASE and the register offset.
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#define | CAN_COER_OFFSET 0xCE |
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#define | CAN_COER_TYPE uint8_t |
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#define | CAN_COER CANREG(COER) |
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#define | CAN_COER_OE 0 |
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#define | CAN_CTRLR_OFFSET 0x00 |
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#define | CAN_CTRLR_TYPE uint8_t |
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#define | CAN_CTRLR CANREG(CTRLR) |
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#define | CAN_CTRLR_INIT 0 |
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#define | CAN_CTRLR_IE 1 |
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#define | CAN_CTRLR_SIE 2 |
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#define | CAN_CTRLR_EIE 3 |
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#define | CAN_CTRLR_DAR 5 |
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#define | CAN_CTRLR_CCE 6 |
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#define | CAN_CTRLR_TEST 7 |
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#define | CAN_STATR_OFFSET 0x02 |
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#define | CAN_STATR_TYPE uint8_t |
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#define | CAN_STATR CANREG(STATR) |
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#define | CAN_STATR_LEC_MASK (0x07) |
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#define | CAN_STATR_TXOK 3 |
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#define | CAN_STATR_RXOK 4 |
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#define | CAN_STATR_EPASS 5 |
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#define | CAN_STATR_EWARN 6 |
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#define | CAN_STATR_BOFF 7 |
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#define | CAN_ERRCNTH_OFFSET 0x05 |
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#define | CAN_ERRCNTH_TYPE uint8_t |
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#define | CAN_ERRCNTH CANREG(ERRCNTH) |
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#define | CAN_ERRCNTH_RP 7 |
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#define | CAN_ERRCNTH_REC_MASK (0x7f) |
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#define | CAN_ERRCNTL_OFFSET 0x04 |
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#define | CAN_ERRCNTL_TYPE uint8_t |
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#define | CAN_ERRCNTL CANREG(ERRCNTL) |
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#define | CAN_BTR_OFFSET 0x06 |
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#define | CAN_BTR_TYPE uint16_t |
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#define | CAN_BTR CANREG(BTR) |
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#define | CAN_BTR_TSEG2_MASK (0x7000) |
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#define | CAN_BTR_TSEG2_SHIFT (12) |
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#define | CAN_BTR_TSEG1_MASK (0x0f00) |
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#define | CAN_BTR_TSEG1_SHIFT (8) |
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#define | CAN_BTR_SJW_MASK (0x00c0) |
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#define | CAN_BTR_SJW_SHIFT (6) |
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#define | CAN_BTR_BRP_MASK (0x003f) |
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#define | CAN_INTR_OFFSET 0x08 |
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#define | CAN_INTR_TYPE uint16_t |
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#define | CAN_INTR CANREG(INTR) |
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#define | CAN_INTR_STATUS_VALUE 0x8000 |
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#define | CAN_TESTR_OFFSET 0x0A |
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#define | CAN_TESTR_TYPE uint8_t |
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#define | CAN_TESTR CANREG(TESTR) |
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#define | CAN_TESTR_RX 7 |
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#define | CAN_TESTR_TX1 6 |
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#define | CAN_TESTR_TX0 5 |
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#define | CAN_TESTR_LBACK 4 |
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#define | CAN_TESTR_SILENT 3 |
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#define | CAN_TESTR_BASIC 2 |
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#define | CAN_BRPER_OFFSET 0x0C |
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#define | CAN_BRPER_TYPE uint8_t |
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#define | CAN_BRPER CANREG(BRPER) |
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#define | CAN_IF1CREQ_OFFSET 0x10 |
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#define | CAN_IF1CREQ_TYPE uint8_t |
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#define | CAN_IF1CREQ CANREG(IF1CREQ) |
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#define | CAN_IF1CMSK_OFFSET 0x12 |
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#define | CAN_IF1CMSK_TYPE uint8_t |
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#define | CAN_IF1CMSK CANREG(IF1CMSK) |
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#define | CAN_IF1MSK_OFFSET 0x14 |
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#define | CAN_IF1MSK_TYPE uint32_t |
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#define | CAN_IF1MSK CANREG(IF1MSK) |
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#define | CAN_IF1ARB_OFFSET 0x18 |
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#define | CAN_IF1ARB_TYPE uint32_t |
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#define | CAN_IF1ARB CANREG(IF1ARB) |
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#define | CAN_IF1MCTR_OFFSET 0x1C |
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#define | CAN_IF1MCTR_TYPE uint16_t |
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#define | CAN_IF1MCTR CANREG(IF1MCTR) |
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#define | CAN_IF1DTA_OFFSET 0x1E |
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#define | CAN_IF1DTA_TYPE uint32_t |
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#define | CAN_IF1DTA CANREG(IF1DTA) |
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#define | CAN_IF1DTB_OFFSET 0x22 |
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#define | CAN_IF1DTB_TYPE uint32_t |
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#define | CAN_IF1DTB CANREG(IF1DTB) |
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#define | CAN_IF2CREQ_OFFSET 0x40 |
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#define | CAN_IF2CREQ_TYPE uint8_t |
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#define | CAN_IF2CREQ CANREG(IF2CREQ) |
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#define | CAN_IF2CMSK_OFFSET 0x42 |
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#define | CAN_IF2CMSK_TYPE uint8_t |
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#define | CAN_IF2CMSK CANREG(IF2CMSK) |
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#define | CAN_IF2MSK_OFFSET 0x44 |
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#define | CAN_IF2MSK_TYPE uint32_t |
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#define | CAN_IF2MSK CANREG(IF2MSK) |
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#define | CAN_IF2ARB_OFFSET 0x48 |
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#define | CAN_IF2ARB_TYPE uint32_t |
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#define | CAN_IF2ARB CANREG(IF2ARB) |
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#define | CAN_IF2MCTR_OFFSET 0x4C |
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#define | CAN_IF2MCTR_TYPE uint16_t |
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#define | CAN_IF2MCTR CANREG(IF2MCTR) |
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#define | CAN_IF2DTA_OFFSET 0x4E |
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#define | CAN_IF2DTA_TYPE uint32_t |
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#define | CAN_IF2DTA CANREG(IF2DTA) |
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#define | CAN_IF2DTB_OFFSET 0x52 |
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#define | CAN_IF2DTB_TYPE uint32_t |
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#define | CAN_IF2DTB CANREG(IF2DTB) |
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#define | CAN_IFCREQ_BUSY 15 |
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#define | CAN_IFCMSK_WRRD 7 |
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#define | CAN_IFCMSK_MASK 6 |
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#define | CAN_IFCMSK_ARB 5 |
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#define | CAN_IFCMSK_CONTROL 4 |
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#define | CAN_IFCMSK_CIP 3 |
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#define | CAN_IFCMSK_TXREQ 2 |
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#define | CAN_IFCMSK_DATAA 1 |
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#define | CAN_IFCMSK_DATAB 0 |
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#define | CAN_IFMSK_MXTD 31 |
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#define | CAN_IFMSK_MDIR 30 |
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#define | CAN_IFMSK_MSK_MASK (0x1fffffffL) |
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#define | CAN_IFARB_MSGVAL 31 |
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#define | CAN_IFARB_XTD 30 |
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#define | CAN_IFARB_DIR 29 |
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#define | CAN_IFARB_ID_MASK (0x1fffffffL) |
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#define | CAN_IFMCTR_NEWDAT 15 |
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#define | CAN_IFMCTR_MSGLST 14 |
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#define | CAN_IFMCTR_INTPNT 13 |
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#define | CAN_IFMCTR_UMASK 12 |
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#define | CAN_IFMCTR_TXIE 11 |
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#define | CAN_IFMCTR_RXIE 10 |
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#define | CAN_IFMCTR_RMTEN 9 |
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#define | CAN_IFMCTR_TXRQST 8 |
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#define | CAN_IFMCTR_EOB 7 |
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#define | CAN_IFMCTR_DLC_MASK (0x000f) |
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#define | CAN_TREQR_OFFSET 0x80 |
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#define | CAN_TREQR_TYPE uint32_t |
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#define | CAN_TREQR CANREG(TREQR) |
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#define | CAN_NEWDT_OFFSET 0x90 |
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#define | CAN_NEWDT_TYPE uint32_t |
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#define | CAN_NEWDT CANREG(NEWDT) |
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#define | CAN_INTPND_OFFSET 0xA0 |
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#define | CAN_INTPND_TYPE uint32_t |
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#define | CAN_INTPND CANREG(INTPND) |
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#define | CAN_MSGVAL_OFFSET 0xB0 |
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#define | CAN_MSGVAL_TYPE uint32_t |
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#define | CAN_MSGVAL CANREG(MSGVAL) |
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