16FXlib
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Macros | |
#define | SEG0_PORT_DB PDR00 |
Port of the first 7seg. | |
#define | SEG0_PORT_DDR DDR00 |
Data direction register for the first 7seg. | |
#define | SEG1_PORT_DB PDR09 |
Port of the second 7seg. | |
#define | SEG1_PORT_DDR DDR09 |
Data direction register for the second 7seg. | |